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| ICS650-40 ETHERNET SWITCH CLOCK SOURCE Description The ICS650-40 is a clock chip designed for use in Ethernet Switch applications. Using ICS' patented Phase-Locked Loop (PLL) techniques, the device takes a 25 MHz crystal input and produces various output clock frequencies as listed in Output Select Table. Features * * * * * * * Packaged in 16-pin TSSOP Available in Pb (lead) free package Operating voltage of 3.3 V Low power consumption Input frequency of 25 MHz Low long-term jitter 2.5 V to 3.3 V clock outputs Block Diagram VDD 3 VDDOA S1:S0 2 Control Logic CLKA Phase Lock Loop CLKB X1/ICLK 25 MHz crystal or clock X2 Clock Buffer/ Crystal Oscillator 4 GND OE VDDOB Optional tuning crystal capacitors MDS 650-40 C I n t e gra te d C i r c u i t S y s t e m s 1 525 Race Stre et, San Jo se, CA 9 5126 Revision 060705 te l (40 8) 2 97-12 01 w w w. i c st . c o m ICS650-40 ETHERNET SWITCH CLOCK SOURCE Pin Assignment X1/ICLK VDD GND VDDOA CLKA CLKB VDDOB GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 GND OE GND VDD VDD S1 S0 Output Select Table (MHz) S1 0 0 1 1 S0 0 1 0 1 CLKA (MHz) 127 133 157 189 CLKB (MHz) 127 133 157 189 16-pin (173 mil) TSSOP Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name X1/ICLK VDD GND VDDOA CLKA CLKB VDDOB GND S0 S1 VDD VDD GND OE GND X2 Pin Type Input Power Power Power Connect to +3.3 V. Connect to ground. Pin Description Crystal or clock input. Connect to a 25 MHz crystal or single ended clock. Connect to +2.5 V or +3.3 V. For clock output buffer A only. Output Clock A output with weak pull-down resistor. Output Clock B output with weak pull-down resistor. Power Power Input Input Power Power Power Input Power Connect to +2.5 V or +3.3 V. For clock output buffer B only. Connect to ground. Select pin 0. Select pin 1. Connect to +3.3 V. Connect to +3.3 V. Connect to ground. Output enable tri-states outputs and device is not shut down. Internal pull-up resistor. Connect to ground. Output Crystal connection. Leave unconnected for clock input. MDS 650-40 C In te grated Circuit Systems 2 525 Ra ce Street, San Jose, CA 9512 6 Revision 060705 tel (4 08) 297-1 201 w w w. i c s t . c o m ICS650-40 ETHERNET SWITCH CLOCK SOURCE External Components A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01 F should be connected between VDD and GND pairs. The capacitors should be placed between pins VDD and GND, and VDDO and GND, as close to the device as possible. A 33 series terminating resistor should be used on each clock output if the trace is longer than 1 inch. A 25 MHz fundamental mode parallel resonant crystal should be used with CL=18 pF. On chip capacitors. On Chip capacitors are used for a 18 pF load crystal. Small 2 to 3 pf trimming capacitors are used from pins X1 to ground and X2 to ground to optimize the initial accuracy. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS650-40. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V Rating -0.5 V to VDD+0.5 V 0 to +70C -65 to +150C 125C 260C Recommended Operation Conditions Parameter Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Min. 0 +3.15 Typ. Max. +70 +3.45 Units C V MDS 650-40 C In te grated Circuit Systems 3 525 Ra ce Street, San Jose, CA 9512 6 Revision 060705 tel (4 08) 297-1 201 w w w. i c s t . c o m ICS650-40 ETHERNET SWITCH CLOCK SOURCE DC Electrical Characteristics Unless otherwise specified, VDD=3.3 V 5%, Ambient Temperature 0 to +70C Parameter Operating Voltage Output Operating Voltage Input High Voltage, ICLK Input Low Voltage, ICLK Input High Voltage, S1:S0:OE Input Low Voltage, S1:S0:OE Output High Voltage Output Low Voltage Operating Supply Current IDD at Output Disable Condition(OE low) Short Circuit Current Internal Pull-up Resistor Internal Pull-down Resistor Symbol VDD VDDOA,B VIH VIL VIH VIL VOH VOL IDD Conditions Min. 3.15 2.375 Typ. Max. 3.45 3.45 VDD/2-0.5 Units V V V V V V V V mA mA mA k k Note 1 Note 1 VDD/2+0.5 2 VDD 0.4 IOH = -12 mA IOL = 12 mA No load No load 2 0.4 40 16 35 250 525 IOS RPUP RPD Each output OE pin CLK outputs Note: 1. Nominal switching threshold is VDD/2. AC Electrical Characteristics , VDD = 3.3 V 5%, VDDO = 2.5 - 3.3 V 5%, CL=10 pF Ambient Temperature 0 to +70 C Parameter Input Frequency Output Rise Time Output Fall Time Output Clock Duty Cycle Frequency Error Output to Output Skew between clocks of the same frequency Absolute Jitter, Short-term P-P Absolute Jitter, Short-term C-C Long-term Jitter Symbol tOR tOF Conditions 20% to 80% of VDD 80% to 20% of VDD at VDD/2 all clocks Min. Typ. 25 1.6 1.6 Max. Units MHz ns ns 60 250 % ppm ps 40 49-51 0 variation from mean 1000 clock cycles 100 200 250 200 400 400 ps ps ps MDS 650-40 C In te grated Circuit Systems 4 525 Ra ce Street, San Jose, CA 9512 6 Revision 060705 tel (4 08) 297-1 201 w w w. i c s t . c o m ICS650-40 ETHERNET SWITCH CLOCK SOURCE Thermal Characteristics (16-pin TSSOP) Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol JA JA JA JC Conditions Still air 1 m/s air flow 3 m/s air flow Min. Typ. 78 70 68 37 Max. Units C/W C/W C/W C/W Marking Diagram 16 9 Marking Diagram 16 9 IC 650G-40 S ###### YYWW IC 650G40LF S ###### YYWW 1 8 1 8 Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. "LF" designates Pb (lead ) free package. 4. Bottom marking: (origin). Origin = country of origin if not USA. MDS 650-40 C In te grated Circuit Systems 5 525 Ra ce Street, San Jose, CA 9512 6 Revision 060705 tel (4 08) 297-1 201 w w w. i c s t . c o m ICS650-40 ETHERNET SWITCH CLOCK SOURCE Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 16 Millimeters Symbol Min Max Inches Min Max Index Area IN D EX AR EA E1 E E H 1 2 Pin 1 DD A A1 A2 b C D E E1 e L aaa -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10 -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004 A 2 A 1 A c a e -C- c e b A L L b S E A T IN G P LA N E aaa C Ordering Information Part / Order Number ICS650G-40 ICS650G-40T ICS650G-40LF ICS650G-40LFT See Page 6 Marking See Page 6 Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Package 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP Temperature 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 650-40 C In te grated Circuit Systems 6 525 Ra ce Street, San Jose, CA 9512 6 Revision 060705 tel (4 08) 297-1 201 w w w. i c s t . c o m |
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